The present invention relates to a test circuit to be built in an electronic circuit formed on a semiconductor device, and a testing method using the circuit.
When there is no defect in a manufactured LSI, it is not necessary to carry out a manufacturing test (hereinbelow, simply called a test). In practice, however, some LSIs are defective due to factors such as dusts during the manufacture.
It is known that, when the cost of finding a defective LSI at a LSI level is taken to be 1, the cost at a board level is 10, that at a system level is 100, and that at a field level is 1000.
From the facts, it can be said that design for testability considering tests from an initial stage of design (stage of LSI) is important.
It is, however, hard to carry out a test on a sequential circuit since observation of the inside from the outside is difficult.
One of the conventional general methods satisfying the requirement of the test is a method of forming a BIST (Built In Self Test) circuit by scanning flip-flops (simply referred to FFs hereinbelow) existing in a sequential circuit and connecting a pattern generator and an expectation value comparator to the scanned circuit.
The scanning of the FF is to change the FF in the sequential circuit to a scanned FF. Specifically, a scan tune is obtained by an external input pin (scan mode: SM). When a clock is added to a clock of an external input (scan clock: T), the FF can be freely set to the FF for writing arbitrary data from the external input pin (scan in: SI). In the case of a structure capable of monitoring an output of each FF from the external output pin (scan out: SO), that is, by replacing the FF with a scanned FF, observability and controllability are increased to enable a test to be carried out.
An example of a full scan will be shown concretely. A circuit as shown in FIG. 12 is changed to have the construction as shown in FIG. 13 to realize a full scan.
A circuit having the construction of FIG. 14 is formed by providing the scan circuit with a pattern generator and an output value compressor. A test is carried out by outputting compressed, values for all patterns from the pattern generator and monitoring whether the internal state changes according to the expectation value by comparing the compressed value and a prepared expectation value with a tester.
With respect to the scanning of a circuit, when a normal FF (FIG. 15) is compared with a scan FF (FIG. 16), the scan FF has a more complicated structure and a larger area is accordingly required to realize the scan FF. The scan FF has drawbacks of a large chip area and a low operational speed.
Further, in the conventional structure, a large number of expectation values have to be prepared for a test. Therefore, in order to form an expectation value comparator in a LSI, a memory which stores a large number of expectation values has to be prepared inside or outside of the LSI.
Though a method of developing a test method and a test circuit for each circuit to be tested to form a BIST without scanning FFs conventionally exists, there is no adequate technique for the design of the BIST. Following are the problems of the method.
(1) Since a BIST circuit has to be designed for each circuit to be tested, it requires effort for designing.
(2) Depending on a design, a very large chip area is required.
(3) There is no guarantee that a BIST for a random logic circuit can have a high failure detection ratio.
It is an object of the invention to provide a built-in self-test circuit and a test method capable of relatively easily carrying out a self-test with a simple circuit construction on the basis of predetermined arithmetic operations by operational elements built in a semiconductor device.
According to one aspect of this invention, in a built-in self-test circuit, an operational element is allowed to perform an arithmetic operation by a test signal generated by a signal generator to obtain a signal value for comparison which is fundamentally equal to the test signal value of the signal generator, and a test result is obtained by comparing the test signal value and the signal value for comparison.
According to another aspect of the invention, a built-in self-test circuit carries out a test by applying a predetermined test signal by a signal generator to two or more operational elements. The operational elements are allowed to perform arithmetic operations to obtain a signal value for comparison which is fundamentally equal to the test signal value, and a test result is obtained by comparing the test signal value with the signal value for comparison.
Further, in the built-in self-test circuit a signal generator generates a signal having first and second signal values; an adder adds the first and second signal values generated from the signal generator; a subtracter subtracts the second signal value of the signal generator from the arithmetic operation result of the adder; and a comparator derives a test result by comparing the arithmetic operation result of the subtracter with the first signal value of the signal generator.
Further, in the built-in self-test circuit: a signal generator generates a signal having first and second signal values; a subtracter subtracts one of the first and second signal values generated from the signal generator from the other value; an adder adds the arithmetic operation result of the subtracter and the other one of the first and second signal values from the signal generator; and a comparator derives a test result by comparing the arithmetic operation result of the adder with one of the first and second signal values of the signal generator.
According to still another aspect of the invention, a built-in self-test circuit carries out a test by applying a predetermined test signal by a signal generator to the two or more operational elements. The operational elements are allowed to perform arithmetic operations to obtain an arithmetic operation result which is fundamentally equal to the test signal value, and a test result is obtained by comparing the test signal value with the arithmetic operation result.
Further, in the built-in self-test circuit: a signal generator generates a signal having a predetermined signal value; an incrementer increments the signal value generated from the signal generator; a decrementer decrements an output value of the incrementer; and a comparator derives a test result by comparing an output value of the decrementer with a signal value of the signal generator.
Further, in the built-in self-test circuit: a signal generator generates a signal having a predetermined signal value; a decrementer decrements a signal value generated from the signal generator; an incrementer increments an output value of the decrementer; and a comparator derives a test result by comparing an output value of the incrementer with a signal value of the signal generator.
According to still another aspect of the invention, a built-in self-test circuit carries out a test by applying a predetermined test signal by a signal generator to two or more operational elements. The operational elements are allowed to perform arithmetic operations to obtain an arithmetic operation result which is fundamentally equal to the test signal value, and a test result is obtained by comparing the test signal value with the arithmetic operation result.
Further, in the built-in self-test circuit: a signal generator generates a signal having first and second signal values; a multiplier multiplies the first and second signal values generated from the signal generator by each other; a divider divides the arithmetic operation result of the multiplier by one of the first and second signal values of the signal generator; and a comparator derives a test result by comparing the arithmetic operation result of the divider with the other one of the first and second signal values of the signal generator.
Further, in the built-in self-test circuit: a signal generator generates a signal having first and second signal values; a divider divides one of the first and second signal values generated from the signal generator by the other one; a multiplier multiplies the arithmetic operation result of the divider by the other one of the first and second signal values of the signal generator; and a comparator derives a test result by comparing the arithmetic operation result of the multiplier with one of the first and second signal values of the signal generator.
Further, in the built-in self-test circuit: an adder adds the same signal value as a predetermined signal value to the predetermined signal value; and an arithmetic circuit reduces an input value to the half. The adder and the arithmetic circuit are allowed to perform arithmetic operations of which result is fundamentally equal to the signal value, and a test result is obtained by comparing the arithmetic operation result with the signal value.
Further, in the built-in self-test circuit: an adder adds the same signal value as a signal value of a signal generator to the signal value; an arithmetic circuit receives the arithmetic operation result of the adder and reduces the input value to the half to obtain an arithmetic operation result fundamentally equal to the signal value of the signal generator; and a test result is obtained by comparing the arithmetic operation result of the arithmetic circuit with the signal value of the signal generator.
Further, in the built-in self-test circuit: an arithmetic circuit receives a signal from a signal generator and reducing the input value to the half; an adder adds the same signal value as an output value of the arithmetic circuit to the output value and obtains an arithmetic operation result which is fundamentally equal to the signal value of the signal generator; and a test result is obtained by comparing the arithmetic operation result of the adder with the signal value of the signal generator.
Further, in the built-in self-test circuit: a complement generator receives a signal value of the signal generator and outputs a complement on the input value; a subtracter performs subtraction between the signal value of the signal generator and the output value of the complement generator; an arithmetic circuit receives an arithmetic operation result of the subtracter and reduces the input value to the half to obtain an arithmetic operation result which is fundamentally equal to the signal value of the signal generator; and a comparator derives a test result by comparing the arithmetic operation result of the arithmetic circuit with the signal value of the signal generator.
Further, in the built-in self-test circuit comprises: a multiplier multiplies a signal value of the signal generator by a signal value xe2x80x9c2xe2x80x9d; an arithmetic circuit receives an arithmetic operation result of the multiplier and reduces the input value to the half to obtain an arithmetic operation result which is fundamentally equal to the signal value of the signal generator; and a comparator derives a test result by comparing the arithmetic operation result of the arithmetic circuit with the signal value of the signal generator.
Further, in the built-in self-test circuit: a divider divides a signal value of the signal generator by a signal value xe2x80x9cxc2xdxe2x80x9d; an arithmetic circuit receives an arithmetic operation result of the divider and reduces the input value to the half to obtain an arithmetic operation result which is fundamentally equal to the signal value of the signal generator; and a comparator obtains a test result by comparing the arithmetic operation result of the arithmetic circuit with the signal value of the signal generator.
Further, in the built-in self-test circuit: a signal generator generates a signal having first and second signal values; an adder adds the first and second signal values generated from the signal generator; a complement generator receives the second signal value of the signal generator and outputs a complement on the input value; a subtracter subtracts the output value of the complement generator from the arithmetic operation result of the adder to obtain an arithmetic operation result which is fundamentally equal to the first signal value of the signal generator; and a comparator derives a test result by comparing the arithmetic operation result of the subtracter with the first signal value of the signal generator.
According to still another aspect of the invention, a built-in self-test circuit carries out a test by applying a predetermined test signal by a signal generator to an operational element. The operational element is allowed to perform an arithmetic operation of which result is fundamentally equal to a predetermined value, and a test result is obtained by checking whether the arithmetic operation result is a predetermined value or not.
According to still another aspect of the invention, a built-in self-test circuit carries out a test by applying a predetermined test signal by a signal generator to an operational element. The operational element is allowed to perform an arithmetic operation of which result is fundamentally zero, and a test result is obtained by checking whether the arithmetic operation result is zero or not.
Further, in the built-in self-test circuit: a complement generator receives a signal value of the signal generator and outputs a complement on the input value; and an adder adds the signal value of the signal generator and an output value of the complement generator and performs an arithmetic operation of which result is fundamentally zero. In the circuit, a test result is obtained by checking whether the arithmetic operation result is zero or not.
Further, in the built-in self-test circuit: a subtracter subtracts the same signal value as a signal value of the signal generator from the signal value of the signal generator so that an arithmetic operation result is fundamentally zero. In the circuit, a test result is obtained by checking whether the arithmetic operation result is zero or not.
According to still another aspect of the invention, a built-in self-test circuit carries out a test by applying a predetermined test signal to the operational element. The operational element is allowed to perform an arithmetic operation of which result is fundamentally equal to xe2x80x9c1xe2x80x9d, and a test result is obtained by checking whether the arithmetic operation result is xe2x80x9c1xe2x80x9d or not.
Further, in the built-in self-test circuit, two or more operational elements have a pipeline construction and shift registers of the number corresponding to the number of stages of the pipeline are provided.
According to still another aspect of the invention, in a test method, a test is carried out by applying a predetermined test signal generated from a signal generator which is either built in a semiconductor device or prepared outside of the semiconductor device to an operational element in the semiconductor device. Two or more operational elements are allowed to perform an arithmetic operation of which result is fundamentally equal to the test signal value, and a test result is obtained by comparing the test signal value with the arithmetic operation result.
According to still another aspect of the invention, in a test method, a test is carried out by applying a predetermined test signal generated from a signal generator which is either built in a semiconductor device or prepared outside of the semiconductor device to an operational element in the semiconductor device. An operational element is allowed to perform an arithmetic operation of which result is fundamentally equal to zero, and a test result is obtained by checking whether the arithmetic operation result is zero or not.
According to a still another aspect of the invention, in a test method, a test is carried out by applying a predetermined test signal generated from a signal generator built in a semiconductor device to an operational element of the semiconductor device. An operational element is allowed to perform an arithmetic operation of which result is fundamentally equal to xe2x80x9c1xe2x80x9d, and a test result is obtained by checking whether the arithmetic operation result is xe2x80x9c1xe2x80x9d or not.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.